Multi-port memories are widely used in electronic applications in which high-speed data transfer is critical, including, but not limited to, data (e.g., packet) buffering, video processing, data communications, shared memory switching, shared link tables, etc. Multi-port memory, unlike its single-port memory counterpart, is generally characterized by its ability to read data from or write data to the memory on one port while simultaneously reading a second piece of data from or writing a second piece of data to the memory on another port. Hence, each port provides a separate independent read and write access path for reading data from the memory or writing new data into the memory. One embodiment of a multi-port memory is a four-port memory, such as a two-port read, two-port write (2R2W) memory, which has dedicated read and write ports.
Multi-port memory is typically implemented using static random access memory (SRAM). In a conventional single-port architecture, each bit in an SRAM cell is stored using four transistors that form two cross-coupled inverters operative as a storage element of the memory cell. Two additional transistors serve to control access to the storage element during read and write operations. A typical SRAM cell uses six transistors and is thus often referred to as a 6T SRAM. In a multi-port architecture, two additional access transistors are generally used for each additional port; hence two-port functionality would be provided by an eight-transistor (8T) SRAM, three-port functionality would be provided by a ten-transistor (10T) SRAM, and so on. A direct implementation of a two-port read, two-port write (2R2W) memory requires a four-port bit cell as well as four corresponding word lines and four corresponding bit lines, resulting in large area consumption, high power consumption, and likely slower performance compared to a single-port memory having the same storage capacity. Because implementing a true monolithic multi-port memory can consume a significant amount of area and power on an integrated circuit (IC) chip, there have been various proposed memory architectures which employ single-port memory cells, often referred to as single port read/write (1RW) memories, each having their own inherent disadvantages.